Hi,
I am digital design engineer,
I have a broad knowledge of digital design in ASIC and FPGA using both VHDL and Verilog.
I am using Vivado, ISE, and Quartus for FPGA, using DC, ICC, and prime-time for ASIC. and UVM for verification.
regarding your projcet, I have worked in many projects related to MIPS, currently I am working on a 7 stage pipline MIPS which uses a hazard unit and a forwarding unit to manage hazards.
I will provide you with a clear explanation of each part of the code, and I will teach you how to make it yourself
I can deliver in a week or 10 days max
Please contact me to know more about your needs.
Regards,
moaaz.