I have design various encryption and authentication function applied to high speed communication chips as a chip architect. I can not only deliver the design to you but also prepare a design document to help you understand the working theory of SHA256.
Here is the sample of my micro architecture:
1. Message Padding
For message M with length l, pad M to MP = {l’hM, 1, k’h0, 64’hl} so (l + 1 + k) % 512 = 448
0 ≤ k ≤ 511
(l + 1 + k + 64) / 512 = N
MP can be divided to N message block MP = {M(1), M(2), …, M(n)}
2. Message Schedule
Message schedule 32-bit word W0 , W1 , …, W63 for ith message block M(i)
0 ≤ t ≤ 15, Wt = M(i)t
16 ≤ t ≤ 63, Wt = σ1{256}(Wt-2) + Wt-7 + σ0{256}(Wt-15) + Wt-16
σ1{256}(X) = ROTR17(X) Λ ROTR19(X) Λ SHR10(X)
σ0{256}(X) = ROTR7(X) Λ ROTR18(X) Λ SHR3(X)
ROTR : rotate to the right
SHR : shift to the right