magic VLSi
$10-30 USD
착불
Sketch a transistor-level schematic of a CMOS 3-input XOR gate.
1- Size the transistors Use the smallest integer widths to achieve ratio of 1(i.e. equal rising
and falling resistances)
2- Use Magic VLSI layout tool to Design your layout of the sized design then use irsim to
simulate your design (all combinations of input A,B,C).
The report should include the following.
Design document
Testing results
Source code and layout
프로젝트 ID: #16601439
프로젝트 소개
수상자:
Hi, I am an electronics and IC layout engineer (not pcb) Magic layout is fine for me... but if you want I can provide simulation data and layout designed in Cadence Virtuoso(a worldwide used soft for layout design an 기타
이 일자리에 대한 프리랜서 5 명의 평균 입찰가: $39
hi, i am electrical engineer, i can do your project on Magic VLSI, plz share its details,,,,.,.,.,.,.
Past 2 years I have worked with various Electrical & Electronic support companies as an Engineer which develop my skills in awarding with excellent, effective & efficient results as per my jobs responsibility. I am in 기타
Hi , I am Electronic Engineer , i can do that by high quality for you , and the best price ,at 2 days contact me if u agree
