need to simulate sim-outorder simulator from simplescalar suite. You will need a unix system for this exercise.

The simulator can be downloaded from here: [login to view URL] You need to download [login to view URL] file The benchmarks can be downloaded from here: [login to view URL] (you need to download only the benchmark assigned to you which we have specified as the Google-classroom comment). Except the benchmark, remaining parameters are same for all students. In other words, each student needs to run benchmark with cache configuration specified for him/her (note that due to this, each student will get different results). Run sim-outorder for 10,000,000 instructions with cache configuration given for you and the benchmark given to you. (Other than these, you don't need to change any parameter). L2 cache block size is 64B and L2 associativity is 8 throughout this exercise. (a) Find the L2 cache miss-rate (=L2_misses/L2_references). Call it DefaultL2MissRate. (b) Find out the IPC (instruction per cycle). Call it BaselineIPC. (Here L1 latency = 1 cycle and L2 latency = 6 cycles). (c) Now increase the latency of L1 cache (both IL1 and DL1) to 2 cycle and get IPC and call it slowL1IPC. (d) Bring back latency of L1 cache to 1 cycle. Increase latency of L2 cache (which is data/instruction unified, so just change DL2 latency) to 7 cycle. Get IPC and call it slowL2IPC. (e) Bring back L1 and L2 latency to their default values. Now change L2 replacement policy to random and FIFO and get L2 miss_rate with each of them. Call them RandomMissRate and FIFOMissRate, respectively. (f) Bring back L2 replacement policy to LRU. Now, find IPC on changing issue policy to in-order, call it InOrderIPC. (g) Bring back the issue policy to its original value. Change instruction decode, issue and commit bandwidth to 8, 8, 8, respectively. Find the new IPC, call it DiffWidthIPC