Design a multi-cycle implementation of the reduced MIPS architecture and implement it on the DE2-115 board.

종료 등록 시간: 6년 전 착불
종료 착불

esign a multi-cycle implementation of the reduced MIPS architecture and implement it on the DE2-115 board. You will need to add I/O to the approach discussed in the text. Add the following peripherals: interrupt system connected to a push button, slide switches, green LEDs, red LEDs, and the 7-segment display. Develop a test program to verify you machine works and run it on the simulator and on the board.

The design can be based on the system in the text but you should maximize the use of behavioral code as opposed to the approach used in the text. The control unit and the alu should be done behaviorally at a minimum.

Provide a report which documents your design, implementation and results. Include data from simulations in the form of screen captures, photos, etc.

Verilog / VHDL

프로젝트 ID: #15578566

프로젝트 소개

6 건(제안서) 재택 근무형 프로젝트 서비스 이용 중: 6년 전

이 일자리에 대한 프리랜서 6 명의 평균 입찰가: $173

ahmedmohamed85

Dear sir I already have the Altera DE2-115 board, please check my profile, I can implement the MIPS on my board and test it, please message me so that we can discuss best regards

$200 USD (3일 이내)
(337 리뷰)
7.7
raulbehl

Hello! I am an experienced Engineer and have been helping out many on this platform. It would be great if I could help you out. Thank you! Relevant Skills and Experience Verilog - 3+ years MIPS - 3+ years Proposed Mi 기타

$155 USD (4일 이내)
(54 리뷰)
5.8
quandangvan

A proposal has not yet been provided

$150 USD (5일 이내)
(7 리뷰)
4.2
sajjadahmed19

I am interested in this project if it requires verilog implementation

$100 USD (4일 이내)
(6 리뷰)
3.1
haykberd

A proposal has not yet been provided

$277 USD (15일 이내)
(0 리뷰)
0.0