Help with VHDL

I have to implement a pipelined DLX processor. I have already constructed the single staged processor. However, I will need you to do the pipelining part which would include the pipelined control, and relevant harard detectors, forwarding unit, and bypassing mechanisms. The project now has been implemented using a supermodular approach where I have tried to make the VHDL codes for the smallest units and then built them upwards in the schematic. I will need the schematic of the pipelined dlx too. here is the drive link with all the files for your reference [login to view URL] I have a certain benchmark to run which i will share once i get to design it but the i will need the isim simulations of the entire processor as a proof that everything works. If there are any other further questions do not hesitate to contact me. If you need me to do some bits and pieces i could do that too. I want to be involved in this as I would like to complete the project that i started and some extra work at the university is preventing me from giving the time it needs. Your help will be greatly appreciated.