Hi,
I hope you are doing well and enjoying digital design.
I believe implementing a design right form modeling until verifying it on an FPGA is always a very special experience.
Throughout my 3+ years of experience in the field, I had the joy of designing and implementing a part of LTE's physical layer right from the Matlab model, through RTL coding, simulations, and back-end stages. I also built many other designs such as a MIPS processor design, Can satellite, and a UART transmitter and receiver. All my designs were verified successfully on either Xilinx's Spartan S6, S3, or Altera's Cyclone V FPGA.
The process of building some RTL design differs according to the final destination of the project. For instance, a design for ASIC tape-out will have other methodologies of debugging and verification than if it's for FPGA.
Subsequently, I would like to know which methodology of testing you would prefer me to adopt, simulations or UVM environments. It is up to you really. I am fine with both.
I would love to hear your thoughts and requirements for the delivery as well.
I wish you get the best out of this project.
- Eslam