Simulating Multiple Gates third installment c + verilog
$60 CAD
착불
The first installment of the project dealt with the capability to simulate the actions of four very simple gate types, an INV gate, an AND gate, an OR gate and an XOR (exclusive or) gate. The second installment extended that capability by describing the simple logic gates using Verilog, but the Verilog was restricted to descriptions of circuits which only contained a single gate. For the third installment, we will allow our Verilog circuits to contain multiple gates
프로젝트 ID: #22267786
프로젝트 소개
이 일자리에 대한 프리랜서 9 명의 평균 입찰가: $60
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