Translate Verilog Project -> VHDL
$10-30 USD
착불
I would like to translate a project written in VERILOG into VHDL. The project consist in reading the ambient temperature using the Nexys4 DDR board and display it on monitor using VGA. The communication between the board and sensor uses I2C protocol. The task would be just to rewrite 2 verilog files into vhdl, synthesis and implement them using xilinx vivado
프로젝트 ID: #10347485
프로젝트 소개
이 일자리에 대한 프리랜서 8 명의 평균 입찰가: $45
Hi , I am working as FPGA design engineer since last 6 years and I have expertise in both verilog and VHDL. I can convert the project from verilog to VHDL. Can your provide me the files because that will give me exa 기타
This is easy stuff , moreover I am intrested to take complete project from you :) as I can prove my code on board. Thanks SK
Hello, I am an Electronics Engineer and also FPGA based digital system designer. I have designed many FPGA based digital systems using Xilinx and Actel FPGA.
I am a highly motivated design engineer who has been employed in the relevant field for 4 ½ years. I have just completed a 15 month contract as a satellite system engineer for the SUPARCO space agency and now seeking m 기타
I have 2 years of experience of working on HDLs. Have written I2C codes in Verilog and VHDL as well. I can complete the job in 1 day.