This project is quite simple and straight forward. I can complete this project within a day! I'm happy to discuss about the project.
Relevant Skills and Experience
I have experience in VHDL and Verilog.
Proposed Milestones
₹1000 INR - VHDL source file, VHDL test bench, Waveforms, Sample Input file, Sample Output file
Additional Services Offered
₹400 INR - Can implement in xilinx vivado and share you the utilization area, worst negative slack