VHDL expert needed
$30-250 USD
착불
Design a serial communication protocol i.e., telegram containing data bus, address bus, read/write bus and checksum(CRC).
1. read/write access is to be transferred. If CPU is doing a write access, then it should have 1 byte address and 1 byte data and control bits if possible.
2. Read bus should read the address to be transferred.
3. The write bus should transfer the PSS signal or the chip select signal for the peripheral boards.
4. PSS is of 16 bits and the status of PSS signal should also be transferred.
5. The data should be on write access for front transfer and on read access for reverse transfer.
6. Define the type of telegram as read or write type.
7. Checksum should check if the data is valid or not.
프로젝트 ID: #28995468
프로젝트 소개
이 일자리에 대한 프리랜서 8 명의 평균 입찰가: $221
Hello, I am digital design engineer with +5 years of experience in VHDL/Verilog. I have worked on a serial protocol which is similar to yours (has address bits, embeds synchronization bits and CRC16 bits to the stream, 기타
Hi, there I am a VHDL and FPGA expert, I can complete your project perfectly and provide live explanation. Contact me to discuss more