An RTL and FPGA design engineer having working in corporate in last 3 years.
Associated with various Projects related to digital design ASIC/FPGA.
HDL Languages known : Verilog,VHDL
Protocols like : I2C,SPI,UART, Amba Protocols APB,AHB,AXI protocol.
Projects done : MIPI Alliance version 3
Made Microarchitecture Design for master and slave IP
FPGA Project :- Joint tactical Networking Centre (Six IP Nodes)
Tools Known : Cadence Ncsim,Xilinx Vivado 2022.1,Cadence Genus,Cadence JasperGold CDC/LINT
Can Teach Synthesis and Static Timing analysis as in Proffessional view.
Any Assignments/Projects related to Design.
I can provide teaching/Coaching also for beginners who want to join VLSI Industry.
Interview Sessions also be Provided.
Greeting of the Day,
Thanks and regards
Sushil kumar