I have 7+ Years of experience in FPGA RTL Design Field,
Developed & implemented 100+ project on various FPGA.
Writting good synthesizable VHDL/Verilog Code,
Implemented it on target FPGA,
Interfaces worked on Ethernet, SPI, UART, I2C.
Worked on Digital Signal Processing, ADC, DAC, FEC Encoding Decoding, Scrambling, TCP/IP, UDP/IP Protocol,
Modulation techniques, BPSK, QPSK,
Developed a FPGA boards using Xilinx Spartan 3, Spartan 6, Artix-7 & Zynq Family.