deisgn and verification of Dynamic/adaptive Huffman code,vitter algorithm using verilog

I am looking to hire someone to go through the vitter algorithm of the dynamic huffman coding and implement the encoder(compulsory) and decoder(optional) . I am willing to explain you the details of the algorithm in depth once we connect . there are several articles that I have referred to but the wikipedia description is pretty accurate so I provide the link here. There is a visual representation of the same algorithm in the other links and some accompanying text explaining. You are required to go through the vitter algorithm and implement the same.

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Verilog / VHDL 전자 공학 전기 공학 FPGA

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