Modify the Code of Simple SPI Master in Verilog
₹600-1000 INR
착불
I have written the code for a simle SPI Master in verilog and also included a testbench. I want you to:
1) Add a Clock Divider to it, so that the output SPI frequecy is 1MHz
2) There are 3 SPI commands: (1) one write command, (2) multiple write command, (3) one read command. Modify the SPI master Verilog code to implement these 3 commands. Ideally, I want to specify (i) write or read, (ii) number of bytes if write command, (iii) address, (iv) data, then the code will automatically generate the correct checksum and dummy bytes.
Would appreciate if the work could be finished as soon as possible. Thanks!
프로젝트 ID: #32566499
프로젝트 소개
이 일자리에 대한 프리랜서 4 명의 평균 입찰가: ₹750
Hi I’m an expert in verilog design and I’m interested in your project I can help you Send me a message to discuss the details
I am a graduated electronics engineer from faculty of engineering Cairo university with very good with honor grade,4 years experience in Verilog, I have done a lot of projects using Verilog &VHDL also my graduation pro 기타
Dear Sir/Madam, I am a senior ASIC design and verification engineer with more than 5 years of experience in complex SoC projects. During my career, I successfully closed verification for several ASIC verification proj 기타
