Hi, I need help creating a Graphical User Interface to be displayed on Multi Touch LCD (MTL Module 2, 800x600 pixel) connected to Altera DE4 Board. There will be five buttons that the user can press/touch and for this project, the user action will be displayed in text. There will also be a circle and a 5x5 table on the GUI.
My project is based on altera monitor program. I need to develop an interactive eye tracking hand synchronization using alters monitor program using bios assembly language only. I need to build an bios hardware using the following components nios classic processor, 2 leds as visual stimulai, seven segment display,pup core,jtag uart,timer ip core. Then u need to used the sof and the sopcinfo file generation to build the custom hardware on altera monitor program. In the project you need to develop an nios program using bios assembly language where it displays hello on the display of fpga de2115 board cyclone 4E only
My project is based on altera monitor program. I need to develop an interactive eye tracking hand synchronization using alters monitor program using bios assembly language only. I need to build an bios hardware using the following components nios classic processor, 2 leds as visual stimulai, seven segment display,pup core,jtag uart,timer ip core. Then u need to used the sof and the sopcinfo file generation to build the custom hardware on altera monitor program. In the project you need to develop an nios program using bios assembly language where it displays hello on the display of fpga de2115 board cyclone 4E only
it uses a FPGA board to program the cpu on it and you should make an audiometer for it using Quartus and NIOS II also you need DE2-115 board the info is in the attachment
Hello ,rnrnFor my Project, we need Data Acquisition from Sensors to DE2-115 Developmental board by FPGA implement EtherCAT slave and via an ADC.rnrnDescription:rnrnWe need to implement an over sampling ADC for an interface between Sensor and the developmental board ( DE2-115). mostly 16 bit. SPI interface is already used, so look for another one.rn There is an CODEC ( WM 8731 ) but audio already available on DE2-115, in case it useful.rnrnThen for Data acquisition, DE 2-115 board need to be implemented as EtherCAT slave, and data to be store in Dual - Port RAM, with bit rate of 40 GBPS, if possible more.rnrnIts a data acquisition project, the data from Sensors are fed to TI controller via FPGA board.rnrnlet me knw,...
Using an Altera De0 Board, I need to create a game using the VGA port. Already started, I want to create a simple matching game 4 by 4 where basically when two objects match, they disappear if they don't, flip back over. Does not have to flip can just be a different color until an object is chosen then show all values. I already have a background created as a sample to what I'd like to create, adding values for the characters. also creating a pointer that allows you to outline the characters on the board. Programs we use - Altera Monitor Program ( debugger ) - C ++ Due by April 7th.
I need someone to do a project for me. plz contact me for more info.
I need someone who is expert on VHDL coding and QSYS. plz contact me for more info.
I need someone who is expert on VHDL coding and QSYS. plz contact me for more info.
Face Recognition using Eigenfaces in FPGA HDL : Verilog Softwares: Modelsim, ALTERA Quartus II FPGA: ALTERA Cyclone II Need to simulate and synthesize eigenfaces for face-recognition in a FPGA. Eigenfaces for recognition by Matthew Turk and Alex Pentland ( IEEE paper) is the core of this project. Eigenfaces method is the core of this project, which is explained in detail in Eigenfaces for recognition by Matthew Turk and Alex Pentland. This method has been implemented successfully in MATLAB and the code is also freely available, but it has not been implemented in FPGA's extensively due to the memory and processing speed constrains. The Pixel information from greyscale face images (up to 5 images can be used & face images should be from approved fa...
Preciso implementar CDN (Cloudflare) em uma loja virtual, mas sem causar impacto referente a precificação. Esta loja tem um sistema de precificação que verifica se o visitante está em SP ou fora de SP e com base nisso altera os valores da loja. Nossa ideia é trabalhar com cache para imagens, js, css e HTML se possível, destruindo o cache sempre que houver uma alteração de preço. O trabalho consiste em implementar o cache na loja e parametrizar o Cloudflare e suas regras.
Tenho esse script : Gostaria de adicionar as seguintes funções: Sistema de reviews e ratings no perfil login via facebook limite troca de mensagem para plano básico botão de upgrade de plano no painel do usuário buscar profissional por CEP Campo CPF na área de cadastro co...net/item/mytalent-portal/18946301?_ga=1.78320276.1253537435.1487082416 Gostaria de adicionar as seguintes funções: Sistema de reviews e ratings no perfil login via facebook limite troca de mensagem para plano básico botão de upgrade de plano no painel do usuário buscar profissional por CEP Campo CPF na área de cadastro com validador (incluindo o fato de após cadastro a pessoa cadastrada não poder alt...
Tenho esse script : Gostaria de adicionar as seguintes funções: Sistema de reviews e ratings no perfil login via facebook limite troca de mensagem para plano básico botão de upgrade de plano no painel do usuário buscar profissional por CEP Campo CPF na área de cadastr...net/item/mytalent-portal/18946301?_ga=1.78320276.1253537435.1487082416 Gostaria de adicionar as seguintes funções: Sistema de reviews e ratings no perfil login via facebook limite troca de mensagem para plano básico botão de upgrade de plano no painel do usuário buscar profissional por CEP Campo CPF na área de cadastro com validador (incluindo o fato de após cadastro a pessoa cadastrada não poder alt...
Embedded device - module finalization & system integration (project modules already 75% complete) Altera SoC DE1 (Dual ARM HPS & Cyclone FPGA) QT HMI Linux on ARM Quartus II for Cyclone NIOS soft processors on FPGA
I need you to develop some software in altera quartus for cyclone IV fgpa
We are developing a new board that has an Altera MAX10 FPGA running an RTOS on Altera's soft-core processor NIOS. We're looking for someone who has experience building an Altera FPGA project and writing code on top of NIOS. Some RTOS experience preferred.
hello i have assignment using altera softwear its due by DECEMBER 5th 2016 Design and implement the logic circuit of a toll booth coin collection system. The system will allow the car to pass through when it receives at least 10 ?. The system will accept, 25 ?, 20 ?, 15 ?, 10 ? , 5? and give the correct change if the driver puts more than the required toll. If you put any design constraints, please specify them in your design. Implement the design using FPGA. Please submit a detail report describing the system including the following: a) Toll collector block diagram. b) All steps in the design process. c) Your VHDL design code. d) The simulation waveforms resulting from the verification of your design. e) The simplified logic schematic of the system.
hello i have assignment using altera softwear my budget 25$ its due by DECEMBER 3rd 2016 Design and implement the logic circuit of a toll booth coin collection system. The system will allow the car to pass through when it receives at least 10 ?. The system will accept, 25 ?, 20 ?, 15 ?, 10 ? , 5? and give the correct change if the driver puts more than the required toll. If you put any design constraints, please specify them in your design. Implement the design using FPGA. Please submit a detail report describing the system including the following: a) Toll collector block diagram. b) All steps in the design process. c) Your VHDL design code. d) The simulation waveforms resulting from the verification of your design. e) The simplified logic schematic of the system.
Hello. I need some help with a project that I have. Please contact me for more details. Thanks.
I am doing project with altera quartus Nios ii tool. In this, we have to interface PS2 keyboard with altera board de2-115f29c7 controller and read the letters from PS2 keyboard on LCD connected on board already. I have interfaced LCD properly and displayed characters by mentioning in program but I am facing problem with PS2 keyboards. Programming is to be done in Embedded C.
Altera board PCIe interface driver using Windows.
Instalar o Wordpress na minha máquina e orientar os primeiros passos ensinando como ver os temas prontos e os primeiros passos para altera-los.<br />Parece que tem que baixar um programa antes, que simularia o servidor de hospedagem.<br />Deixar tudo redondinho e dar algumas dicas de como usar.
Specification: The serdes circuit should take 16 16-bit data from one memory and transfer it to another memory serially. The design will have 2 parts. Following should be the functionality: Part 1 Data from a preset memory (16 locations of 8-bits each) is converted to a serial stream of data and sent out of the FPGA chip through a single pin... Part 2 ...The serial transmission from part 1 is captured and converted to parallel data before being stored in another memory location( as 16 locations of 8-bits). The data in this memory should match with the data in memory in Part 1. Both parts are to be implemented in the same FPGA ....The serial out from part 1 will be physically connected with a wire to the serial input in part 2 (in a loopback configuration) This circuit shoul...
Taking reading from ADC and display it on I2C LCD on Altera MAX10. ADC should be designed using Qsys. MAX10(i2c master) is connected to i2c LCD (Slave) to display the value.
This project require you to design a logic circuit using state machine of ( nim game misere strategy) and implement it using VHDL. The code should be written to run on altera E2_115 board. All detail is elaborated in the attached word document. you should do the following: 1. you must include the de-bouncer VHDL file in your code as a component and use it as it is, no change is allowed inside it. (this file attached). 2. Algorithmic State Machine of the system that you used in your code and the Block diagram of The design . 3. Fully documented VHDL source code 4. Pin assignment file good luck
...passeio: (Altera preço do pacote se a duração do passeio escolhida for superior a duração mínima definida para o pacote) Seleção da data inicial disponível e hora; Seleção da data final disponível e hora. 3) Local do passeio (não altera preço) Inserção ilimitada de locais pela empresa; Seleção de local disponível. 4) Qtd. de passageiros = De 1 até 10 por lancha. (Altera preço) Inserção de passageiros no pacote escolhido. 5) Cardápio (Altera preço) O cliente poderá escolher os itens do cardápio para compor as refeições: entrada/ prato principal /...
Snake Game : 1.) Should run on Altera DE2 Board. 2.) Should Support VGA. 3.)Needed in a week.
I need an electronics engineer with about 2 years of experience in programing FPGA's to discuss the project with me. the FPGA chosen is Altera Cyclone IV. The board shall be connected to a USB port and the circuit diagram and all datasheets shall be provided. the FPGA board takes data from the PC on the USB and forwards it to another electronic board and at the same time manages a few motors ( 3 nos) and about 12 sensors. All details shall be provided to the concerned engineer
Hi, I need a verilog HDL code for a simple project, the project is as follows: you start off as a single blue square on the bottom of the screen(background black), then once the game starts, blocks(red squares) start falling from the top of the screen and you use KEY[1]and Key[2] on the DE2 board as controls to move your square right/left to dodge the falling blocks. if you get hit by a falling block the game terminates and goes back to it's original state(a single blue square at bottom of screen). the below is the vga adapter we use module part1(SW,KEY,CLOCK_50,VGA_R, VGA_G, VGA_B, VGA_HS, VGA_VS, VGA_BLANK, VGA_SYNC, VGA_CLK,LEDR); input CLOCK_50; input [17:0] SW; input [3:0] KEY; output [17:0]LEDR; output [9:0] VGA_R; output [9:0] VGA_G; output [9:0] VGA_B; out...
I am working as a Research Assistant at the University of Applied Sciences Frankfurt, Germany. As a part of a bigger application involving safety assurance systems for banks, I want to implement a Face Recognition System using Local Binary Pattern on Altera-based Cyclone FPGA. I have a working software implementation running on MATLAB but to compare how faster and effective a hardware implementation works, I need a working VHDL Code that employs the Local Binary Pattern operator, where the image captured from a camera is compared with the database stored on a micro-sd card and a corresponding match is found.
Interfacing Mips datapath with the altera DE1-SOC board.
...should be able to make 70-120 live contacts per day and should average 5-8% paid leads on their live contacts. **Company Information and Summary of Sales Calls and Closing: Our corporations ECD business segment does electronic component distribution. We inventory 12 million electronic components of different part numbers made by large semiconductor firms such as Texas Instruments, Xilinx, Altera, Tyco/Amp, and 400 more large semiconductor component manufacturers. We are also publicly marketed on some of the large online chip forums. Our goal is to increase sales by also getting strong inside sales/telemarketers/virtual_sales agents. The telemarketer will contact purchasing agents and buyers from OEM’s and CM’s, introduce our company and capabilities ove...
My project is to transfer data between Hps and Fpga on altera De1 soc board. Fpga side there will be Sdram and from the hps we should be able to read and write the data. The data transfer will be done with through AXI bridges and this hardware part can be designed using Quartus 2 Qsys. Hps can be programmed using C language using altera de-5. Ultimate goal is to transferring data. I am new to this field and don't know exactly what to do. I have created Qsys part( with sdram controller, pll , hps i.e cyclone v , jtag uart) I have successfully created the connections with the master slave AXI Avalon interface. Now don't know how to proceed further.
I have a project that was designed for me. It's been completed from schematic design, PCB design and software. A video of the protype has been shown, so it's a working product. I need someone to load the PCB ( surface mount parts used ), Burn the software onto the PCB which uses an Atmel and Altera device and test both PCBs. There are 2 types of PCBs referred to as a MASTER and a SLAVE. I can supply all related documents for this project. Would like some one in Australia to be able to take on this job but willing to look at other bidders from overseas. The original designer of this project has been uncontactable for the last 12 months and it is URGENT that I start production. This job will be ongoing so it's difficult to set a budget. Budget can be negotiable.
Need to work on Altera De1-Soc board. Need to make communication between HPS and FPGA. Software used are Quartus 2 Qsys.
...impresso, que fosse possível aceder ao bilhete diretamente da plataforma;<br />11. As Notas de encomenda necessitam de ser formatadas corretamente;<br />12. No backoffice, na tabela das reservas (Izzato>Izitours>Reservas) as novas encomendas não estão a entrar nesta listagem e isto é essencial;<br />13. Nos transferes, os nomes dos destinos ultrapassam os limites dos Bilhetes.<br />14. Quando se altera a linguagem da plataforma, os separadores que aparecem estão errados....
I have an Altera DE0 board, we need to read analog signal and generate two streams of output: DAC to audio and PWM to motor control. Then the frequencies of the output signals need to be plotted on LCD screen to see visual image of the two data streams. Beginner-intermediate level work, need project at earliest so priority given to those who have necessary equipment to begin work.
Altera es una empresa dedicada a crear y desarrollar plataformas digitales, con el fin de dar soluciones a los distintos requerimientos de nuestros Mobile busca analista informático o ingeniero informático para nuestra área de desarrollo, en nuestra oficina ubicada en Almirante Pastene, salida Metro Manuel laboral tiempo completo: lunes – viernes de 9:00 a 18:00.¡Si te gustan los desafíos, trabajar en equipo y buscas un grato ambiente laboral, entonces postula!Conocimientos deseables:•Desarrollo en Android (Deseable conocimiento en geolocalización)•Java•SQL Server 2008, 2012•C#, asp.net, Web Services•php Framework Laravel 4.2•MySQL•Javascript•jQuery•Ajax•HTML•datatables•guzzl...
Device: Solarflare AOE card (SFA7942Q) description link : FPGA board: Altera Stratix V A7 Job description: Solarflare FDK provided a complete "Tick to trade" example. It only works on 1 10G port. The FPGA card will keep receiving UDP packets from a server. When it received a interested packet, it sends out a TCP packet back to the server. The detail of this sample is on page 111 of the attached user guide. Modification: 1. 4 port mode We need to modify this example, such that it operates at 4x10G ports mode. The usage of port is as follow: Port 1 (10G): receive UDP packets from source 1 Port 2 (10G): receive UDP packets from source 2 Port 3 (10G): send out TCP packet if interested UDP packet is received Port
Device: Solarflare AOE card (SFA7942Q) description link : FPGA board: Altera Stratix V A7 Job description: Solarflare FDK provided a complete "Tick to trade" example. It only works on 1 10G port. The FPGA card will keep receiving UDP packets from a server. When it received a interested packet, it sends out a TCP packet back to the server. The detail of this sample is on page 111 of the attached user guide. Modification: 1. 4 port mode We need to modify this example, such that it operates at 4x10G ports mode. The usage of port is as follow: Port 1 (10G): receive UDP packets from source 1 Port 2 (10G): receive UDP packets from source 2 Port 3 (10G): send out TCP packet if interested UDP packet is received Port 4 (10G): normal
Device: Solarflare AOE card (SFA7942Q) description link : FPGA board: Altera Stratix V A7 Job description: Solarflare FDK provided a complete "Tick to trade" example. It only works on 1 10G port. The FPGA card will keep receiving UDP packets from a server. When it received a interested packet, it sends out a TCP packet back to the server. The detail of this sample is on page 111 of the attached user guide. Modification: 1. 4 port mode We need to modify this example, such that it operates at 4x10G ports mode. The usage of port is as follow: Port 1 (10G): receive UDP packets from source 1 Port 2 (10G): receive UDP packets from source 2 Port 3 (10G): send out TCP packet if interested UDP packet is received Port 4 (10G): normal
...equipamento), adicionar algumas fotos da instalação do cliente e adicionar as coordenas geográficas do cliente pelo GPS para facilitar o retorno ao cliente no futuro, contendo assim suas coordenadas e endereço para que o google maps o ajude a encontra-lo mais rápido da próxima vez. (Pois no ato do cadastro do cliente algumas informações de endereço sempre veem com alguma informação incorreta, para poder altera-lo e marcar o ponto do GPS para facilitar para o próximo técnico).<br /><br />Necessito no futuro de um APP, para meus clientes acessarem a área do assinante que ali ele vai poder ver seus pagamentos, gerar/atualizar seus boletos bancários, trocar de plano, s...
This is my MSc project. I have to implement on Wavelet Packet Transform and a support vector machine on FPGA. Our University has Altera Cyclone V SoC Dev kits which I want to use as demo board for my project. I have written and simulated MATLAB code for the deign which I can provide to the designer.
We are a team of four Civil Engineers and two Architects, and we are looking for some serious freelancers who can help us promote our drafting services and find some serious projects all over the world and work for commission. We will discuss all details about your earnings and our services in chat when we contact you. Please only serious freelancers should bid, new freelancers are also...Engineers and two Architects, and we are looking for some serious freelancers who can help us promote our drafting services and find some serious projects all over the world and work for commission. We will discuss all details about your earnings and our services in chat when we contact you. Please only serious freelancers should bid, new freelancers are also welcome. Please start your bid with word ...
Alteração de dados de processamento num site. Pretende-se que se coloque dados ou altera-se dados no mesmo site.
Hi ahmedmohamed85, I noticed your profile and would like to offer you my project. We can discuss any details over chat. basically just generating verilog code from openCL code via xilinx or altera software.
