EtherCAT slave implement in VHDL/Verilog.

Hello ,\\r\\n\\r\\nFor my Project, we need Data Acquisition from Sensors to DE2-115 Developmental board by FPGA implement EtherCAT slave and via an ADC.\\r\\n\\r\\nDescription:\\r\\n\\r\\nWe need to implement an over sampling ADC for an interface between Sensor and the developmental board ( DE2-115). mostly 16 bit. SPI interface is already used, so look for another one.\\r\\n There is an CODEC ( WM 8731 ) but audio already available on DE2-115, in case it useful.\\r\\n\\r\\nThen for Data acquisition, DE 2-115 board need to be implemented as EtherCAT slave, and data to be store in Dual - Port RAM, with bit rate of 40 GBPS, if possible more.\\r\\n\\r\\nIts a data acquisition project, the data from Sensors are fed to TI controller via FPGA board.\\r\\n\\r\\nlet me knw, in case of additional details. as am student i afford less.\\r\\n\\r\\nRaja.