...performance problem using PolyPhase Channelizer, which is part of GnuRadio for this purpose. I know that such operations (multiplication, working with vectors and floating-point numbers) fit well on gpgpu and fpga, which means that one single device can potentially cope with this task (as evidenced, for example, by this document and other). In any case, it is more preferable to use gpu because of the availability of them "at hand", at least from my side at the moment. As an option, we think to work with OpenCL. FPGA can be a good option for the final product due to less than gpu power consumption. We work with radar systems, in this project the band is from 80 to 160 MHz with channels in 800 kHz at 4 GHz (100-200 channels)
We need a modification to an Ettus USRP SDR FPGA code. We have a working system and reference for a 1 TX and 1 RX system, using half of the USRP1, including the source files for the FPGA code and corresponding c library. We have working FGPA code for a 2 TX and 2 RX system, and but need about 15 lines of verilog code ported from the 1 TX and 1 RX system to the 2 TX and 2 RX system. Also, we need the working c libary in the transceiver (1 Tx and 1 RX) modified to support the 2 TX and 2 RX configuration, which should require about 20 - 40 lines of c code changes. All work can be completed remotely, and we would make available a reference 1TX and 1RX system (with all source code), and a development environment for the 2TX and 2RX system (where you could test your modified FG...
We would need design and production of FPGA or ASIC units optimized to run just a specific OpenCL program as fast as possible. This OpenCL program calculates cryptographic hash functions and has a benchmark report that displays how many hash calculations are made per second. Your FPGA/ASIC should calculate at least 20 billion hashes per second while executing our OpenCL kernel, and should consume less than 1500W. The software in question is here: and the OpenCL kernel that needs to be executed in hardware by your device is the /zcash/gpu/ source file. We would prefer that you provide OpenCL drivers for Windows 32-bit , but we can discuss the possibility to switch to Linux. The device interface can be USB or PCI-e or other
please check the attached file . I want to complete using quartus tool to install it on fpga altera kit in 3 hrs max
i am looking for the VHDL or Verilog code that have UDP or TCP protocol and can have Lan connection fpga spartan 6 to pc by wiznet W 5300 . anyone can help me for that?
...ZedBoard: 1. Given 256 bit BITKEY, scramble the input with a hard coded IDKEY in the FPGA and provide a AESKEY 2. The same response needs to be piped to an AES256 module from OPEN CORES in order to encrypt/decrypt a stream of data INPUTS: 1. 256 BITKEY 2. selector BIT for encrypt decrypt (the output needs an XOR for decrypt) 3. stream of data as 256 bit 'chunks'. The architecture here should be trivial to support a driver easily. OUPUTS: 1. 256 AESKEY 2. stream of encrypted/decrypted data as 256 'chunks' DOCUMENTATION: This should be the bulk of the work; There needs to be diagrams and specifications for reproduction on another ZedBoard. This should include: 1. Layout of blocks 2. FPGA registers used and how the driver should interac...
FPGA, circuits plan. Projects plan, writings... more in PM
Hi, The vision I have in mind is comparable to a machine vision camera. CMOSIS CMV2000/4000 cmos sensor will be readout over LVDS channels and acquired data compressed with H264 encoder (MPEG 4) and compressed data will be send over GigE and/or USB 3.0. I'm a PCB designer with RF design experience, for this project: 1. Propose design architecture ( Pure FPGA, FPGA+controller, DSP or SoC FPGA etc.) 2. PCB Design 3. Software or VHDL project You can quote for total or for each parts.I can design and verify second part myself if it is needed. -1920x1080 (minimum) -Large Pixel Cells 5.5u x 5.5u (CMV2000, CMV4000 sensors) -50 fps (minimum, optional 150 fps) -MPEG 4 compressed over GigE and/or USB3.0 interface
FPGA 医疗成像，和视频融合 ，可视化KVM ，video wall 视频处理(Removed by Freelancer.com Admin)
I need to design a PCB with an FPGA to talk to multiple cameras over USB C
Looking for an experienced embedded software/firmware engineer with video signal processing know-how. The scope of the project is to program a FPGA board to control a display driver. The FPGA board will receive live continuous video feed from a CMOS camera ASIC. The finished product will allow us to command the display driver to display different variations of the CMOS camera video on an electronic screen.
Looking for algorithm design development specialist / firm for continuous support, in confidence, familiar in data compressions especially with enumerative coding lexicographic Index ranking/unranking, and various entropy coders like Range Coder .... develop algorithms mainly in Visual Studio C# , may need to help port over to C in the future for FPGA or ASICs --- I need you to develop some software for me. I would like this software to be developed for Windows using C# or C++.
We have an electronic schematic of a simple surface mount circuit assembly and we would like you to create firmware on an FPGA to perform some of the functions of the circuit assembly.
ITS FEATURE LEVEL FUSION OF DIFFERENT BIOMETRIC MODALITIES LIKE IRIS, FACE, FINGER PRINT. The design simulation in matlab , implementation on smart phone and fpga is required with technical writing
This is extremely simple but urgent!!! You are asked to provide a simple Xilinx Spartan 6 FPGA program that reads data from multiple I2S input ports and then aggregate them into a single data stream and output through uart or I2s or USB.
Desarrollo de Aplicación LabView en tiempo real sobre FPGA e interfaz en Host.
I need to implement a system which consists of camera, FPGA and screen and this system will detect the total number of faces inside the captured image by camera and show the result on screen. The algorithm used for this is viola-jones algorithm.
Its the same project plz accept it so to share milestone with you. the project is to use that IP as a bridge between wishbone bus and can bus. Ie it will take data from wish bone bus and give it to can bus and similarly it may take data from from Can Bus and put it on Wishbone Bus
I am looking for developer for digital signal Processing , I need VHDL code for : 1- Digital Up converter . 2- Digital Down Converter . 3- SSB , LSB , USB , ISB Modulation / demodulation . 4- AME Modulation/ demodulation 5- FM Modulation/ demodulation . 6- FSK Modulation/ demodulation 7- GMSK Modulation/ demodulation 8- QAM Modulation/ demodulation 9- JESD204 . 10- AES256 .
I need someone expert in ASIC design to design digital clock with VERILOG CODE by Quartus software Contact me for more details
design digital clock with alarm with Verilog code / FPGA
I need some experienced FPGA designer that has a hands on experience on wish bone bus and can bus implementation. the work has to be delivers as soon as possible so only bid only those that has already have implemented the wishbone bus and can bus.
I looking for implementing data transfer from ARM to FPGA at ZYNQ 7000 Family according to Chapter 5 Just to generate two 16bit counters one up and one down and to send the data to any FPGA parallel port at rate of at in the least 10MHz
required and experienced electronics system designer to draw architecture and implementation of a bridge circuit in verilog for implementation in FPGA. need the work to be done as soon as possible
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The goal of the project is the conceptual design and implementation of a modular FPGA firmware for multichannel data acquisition which, depending on the connected ADC, configures the FPGA interfaces for the data acquisition via "Partial Reconfiguration" and transmits the data after processing via PCIe to an embedded computer. The firmware is used in a new modular measuring system. The modular measuring system has 5 slots, which are intended for the insertion of ADC boards. The slots have a direct connection to the FPGA I / O banks.
The goal of the project is the conceptual design and implementation of a modular FPGA firmware for multichannel data acquisition which, depending on the connected ADC, configures the FPGA interfaces for the data acquisition via "Partial Reconfiguration" and transmits the data after processing via PCIe to an embedded computer. The firmware is used in a new modular measuring system. The modular measuring system has 5 slots, which are intended for the insertion of ADC boards. The slots have a direct connection to the FPGA I / O banks.
Implementation of Image processing algorithms on FPGA/CPLD hardware using VHDL, and Verilog, MATLAB
Hi, I'm looking to get another freelancer working on PCB design on some projects. Both of my electronics engineers are busy with other projects. I need someone who can design a PCB to get data from an image sensor chip. I'd like to use an FPGA to control the acquisition. The data needs to be relayed to a FT601 chip, then via USB3.0 to a PC. You would also be responsible for making a .dll on the PC side. I'll write software that will call functions from the .dll. The connections between the FPGA and image sensor chip run at quite high frequencies, so care needs to be taken when laying out the PCB. Is this something you think you could help with? Thanks, Andy
It's mostly easy as it is beginner project, but I am new and ...Bare metal code. something to do with DDR3 storage from avalon Bus Requirements: BCLK runs 16MHz1 left and right channel is 16 bits sample each side I have Started the Verilog code, or will provide you with opensource i2s ip. Please do provide me with information how to load on QSYS how to run the testbench to test it's working. This will be my guide to learn how to use Altera and learn FPGA. I'm using a cyclone V SOC (Altera dev kit soc), but any you can implement in other if needed, i can reassign pins later. Resources I have used to help with the idea of I2S. Specs: Tutorial:
transmit data over TCP/IP protocol (1000MB Ethernet). If you have knowledge please bid. Details will be shared in message with the freelancers.
Interfacing an Altera FPGA to a Windows PC to transmit data over TCP/IP protocol (1000MB Ethernet).
FPGA programming and interfacing using T20 collibri module
I need someone to submit some articles for me. Just what makes an FPGA so different from a microcontroller and yet so versatile? This article continues the exploration of FPGAs, focusing on the role of flip-flops and lookup tables (LUTs) in logic blocks
The objective of my project is to implement the Viola-Jones algorithm to detect the number of faces in an input image on FPGA by using VHDL. The input image is saved in BRAM and i need to process the image and detect the total number of faces in that image. The detected faces will be surrounded by the square/rectangle.
The objective of my project is to implement the Viola-Jones algorithm to detect the number of faces in an input image on FPGA by using VHDL. The input image is saved in BRAM and i need to process the image and detect the total number of faces in that image. The detected faces will be surrounded by the square/rectangle.
The objective of my project is to implement the Viola-Jones algorithm to detect the number of faces in an input image on FPGA by using VHDL. The input image is saved in BRAM and i need to process the image and detect the total number of faces in that image. The detected faces will be surrounded by the square/rectangle.
I am looking for a freelancer to help me with my project. The skills required are FPGA, Software Architecture, Software Development and Verilog / VHDL. I am happy to pay a fixed priced and my budget is $250 - $750 USD. I have not provided a detailed description and have not uploaded any files.
Implementar um jogo em verilog ou vhdl em vga
Implement algorithms in Xilinx FPGA writing Verilog / VHDL code to generate optimize RTL and create software to test and characterize the algorithms.
I am looking for a freelancer to help me with my project. The skills required are Algorithm, FPGA, Matlab and Mathematica and Verilog / VHDL. I am happy to pay a fixed priced and my budget is ₹12500 - ₹37500 INR. I have not provided a detailed description and have not uploaded any files.
I am looking for a freelancer to help me with my project. The skills required are FPGA, Software Architecture, Software Development and Verilog / VHDL. I am happy to pay a fixed priced and my budget is ₹12500 - ₹37500 INR. I have not provided a detailed description and have not uploaded any files. and also i am searching for phd project if you have any problem with solution please inform me
I need you to develop some software for me. I would like this software to be developed for Linux using C or C++. Image processing algorithm development using MATLAB and to generate C/C++ and to run the software on FPGA
Hi seshupower, I am an experienced professional in verilog/VHDL design and working on spartan FPGA board since past 10 months. Kindly let me know if you have any freelancing work for me. Thank you
Need to design a CPU talking to an FPGA which has a bunch of Gigabit Ethernet. L2 packet format will be proprietary and packet transfers have strict latency requirements. Logic frequency will be at 125Mhz - 150Mhz. Also need on-site support in bangalore for hardware testing/integration for a week.
I am looking for a freelancer to help me with my project. The skills required are FPGA, DSP, Software defined Radio , RF MODEM, Matlab , Communication, Waveform generate, , and Verilog / VHDL. I am happy to pay a fixed priced and my budget is $250 - $750 USD. I have not provided a detailed description and have not uploaded any files.
Very simple electronic task, i need some advice. I have a push button as the schematic attached, high state value to MCU is 5V. I want to connect same push button to 3.3V FGPA and need suggestion if this could only be solved with resistor NET changing 5V level signals to 3,3V or need other solution. Orange line on the schmeatic is where I want to connect to FPGA PIN. Budget 10USD!
