Hello! I need to convert C++ to matlab simulink model. Finally the simulink model should work on fpga. Please bid here if anybody have experiences in C++ to Simulink to FPGA. Thanks
Hello! I need to convert C++ to matlab simulink model. Finally the simulink model should work on fpga. Please bid here if anybody have experiences in C++ to Simulink to FPGA. Thanks
check the attached pictures please to do this project you have to have the ( same program , same board ) and all I have attached .
You should be very competent in FPGA and DSP, especially for audio signal processing. You should also have worked on MEMS microphone with PDM digital interface. What I need you to do is the following: 1. select a Xilinx FPGA such as Spartan 6 for 2. hooking up 16 MEMS digital microphones with PDM interface 3. simultaneously sampling audio at 16-bit 48KHz 4. send out through USB as USB Audio Your deliverables include: - Electronics (BOM, schematics, PCB layout, etc) - firmware (project, source code, etc) - test package (electronic test points, firmware testing, and computer verification process) Please indicate if you can source all parts (FPGA, MEMS microphone etc) and fabricate PCB on your side within one week. I want to avoid lengthy international ma...
i need help in this project using VHDL program and i need a report with it
i want to monitor power on the fpga board. its MAX 10 NEEK board from altera. The task is to monitor the voltage rails when a load is running on the board. The load will be different video signals being run on the lcd of NEEK board. HDMI in is recieving video from either HDMI player or just directly from a laptop HDMI out .could be a video played on youtube or VLC player. There is a code which displays the video on the LCD successfully. There is another example code for power monitor when there is no load running on the board. Instantiation of one needs to be done with the other.
I have a project in my masters, which is to monitor power on fpga board when different types of load are running on it. Considering the load as different types of video signals. There is an example design available for the MAX10 NEEK which dispalys HDMI input on the LCD screen of the board. There is another example code for power monitoring the voltage rails of the board. I want the combination of both i.e displaying hdmi and monitoring power at the same time
looking for a FPGA have experience on it and good knowledge on VHDl.
looking for a FPGA have experience on it and good knowledge on VHDl.
Hi, Only serious bidders please. Before awarding the project, I will take an interview related to Embedded System Design. Write “I am ready for interview” in your bid so that I should know that you have read my project description, else REJECTED! I need presentations (ppt) on the following: 1. Xilinx Virtex-7 FPGA 2. System Verilog 3. PIC 4. Network on Chip (NoC) 5. AVR Architecture Furthermore, I need ppt converted to pdf of 1. RISC 2. CISC 3. Power PC 4. Multicore Architectures.
...capability), do some rudimentary PID filtering (for example dropping NULL packets), provide (optional) AES128 encryption with fixed key, and ability to stream over PCIe. Host side driver development is NOT needed, however some basic testing will be required to prove the design. I may open another project for the host driver development, unless a reference design driver can be quickly adapted. Target FPGA - Lattice ECP3 w/PCIe IP Using LFE3-35EA-VERSA-EVN Evaluation board (can be dropshipped to user after skill confirmation) mspaint diagram is provided - more details can be explained over chat. Preferably looking for someone who has done PCIe with ECP3 (obviously) and has a general understanding of mpeg transport stream, PID filtering, etc. Budget is flexible, priority i...
EPD-Dev is a development board for driving various electrophoretic displays (EPDs, a.k.a. e-paper displays). The main components of the board are: - Lattice iCE40-4k FPGA (TQFP-144) - Cypress SRAM (TSOP-48) - Cypress SPI Flash PROM holding the FPGA bitstream (SO-8) - TI TPS65185 PMIC (VQFN-48) - Fut. Tech. FT232H USB IC (LQFP-48) Board v1.0 has some errors, the most critical being that the TPS65185 PMIC does not produce the required voltages. There are also minor improvements to be made and we have a small wish-list of changes. Job description: 1. Get acquainted with the design 2. Critically appraise the design and suggest improvements 3. Discuss the errors, minor improvements, and wish-list and decide actions 4. Fix the errors, add the minor improvements, im...
In this project we need to write a code to scan a RGB LED matrix using a spartan FPGA. These LED panels are used to display images and to make LED screens we see in stadiums or outdoor advertisements. Here are some details about its theory of operation: - FPGA has a display frame buffer in it which is regularly updated by the next and next frame to generate a video from other CPU or microcontroller board, and FPGA regularly keeps pushing that frame buffer's data onto the LED panels to show video. You have to write a code to refresh FPGA's internal frame buffer onto the connected LED panel using serial connections. To better under stand the whole thing here we have a exact project example done by someone else which explains everything about the LED...
Hi ahmedmohamed85, I noticed your profile and would like to offer you my project. We can discuss any details over chat.
Need to write a code to control/scan RGB LED panel, using Spartan 6 FPGA board. I have very specific references of same kind to take help from. Just google "RGB LED using FPGA" you will get number of references from internet. However I will also describe brief detailed requirement once we finalise the deal. Price is also negotiable.
I need synthesisable VHDL code for 16 point Fast Fourier Transform that can be implemented on Spartan 3e FPGA
I am looking for a freelancer to help me with my project. The skills required are Algorithm, FPGA, Matlab and Mathematica and Verilog / VHDL. I am happy to pay a fixed priced and my budget is ₹12500 - ₹37500 INR. I have not provided a detailed description and have not uploaded any files.
I am looking for a freelancer to help me with my project. The skills required are Arduino, Embedded Software, FPGA and Microcontroller. I am happy to pay a fixed priced and my budget is €250 - €750 EUR. I have not provided a detailed description and have not uploaded any files.
I am looking for a freelancer to help me with my project. The skills required are Arduino, Bluetooth Low Energy (BLE), FPGA and Microcontroller. I am happy to pay a fixed priced and my budget is $250 - $750 SGD. I have not provided a detailed description and have not uploaded any files.
I am looking for a freelancer to help me with my project. The skills required are FPGA, I Verilog / VHDL. I am happy to pay a fixed priced and my budget is $20 CAD. This mini project is a two traffic light controller with a seven segment display to go with LED outputs.
Hi, I need help creating a Graphical User Interface to be displayed on Multi Touch LCD (MTL Module 2, 800x600 pixel) connected to Altera DE4 Board. There will be five buttons that the user can press/touch and for this project, the user action will be displayed in text. There will also be a circle and a 5x5 table on the GUI.
Hi I need someone to help me with a FPGA project. Step one is to make this board: have some custom resolution capabilities. I think the Xilinx IP goes up to 8K resolution but I'm not sure what it supports or how much it can be customized. Input: 1280x720@60Hz 1920x1080@60Hz 1920x1080@75Hz 1920x1080@120Hz 2160x1200@90Hz 2400x1525@90HZ Output: 1920x1080@60Hz 1920x1080@75Hz 1920x1080@120Hz 2160z1200@90HZ I will discuss the rest of the project with you.
My project is based on altera monitor program. I need to develop an interactive eye tracking hand synchronization using alters monitor program using bios assembly language only. I need to build an bios hardware using the following components nios classic processor, 2 leds as visual stimulai, seven segment display,pup core,jtag uart,timer ip core. Then u need to use...build an bios hardware using the following components nios classic processor, 2 leds as visual stimulai, seven segment display,pup core,jtag uart,timer ip core. Then u need to used the sof and the sopcinfo file generation to build the custom hardware on altera monitor program. In the project you need to develop an nios program using bios assembly language where it displays hello on the display of fpga de2115 board cyclo...
My project is based on altera monitor program. I need to develop an interactive eye tracking hand synchronization using alters monitor program using bios assembly language only. I need to build an bios hardware using the following components nios classic processor, 2 leds as visual stimulai, seven segment display,pup core,jtag uart,timer ip core. Then u need to use...build an bios hardware using the following components nios classic processor, 2 leds as visual stimulai, seven segment display,pup core,jtag uart,timer ip core. Then u need to used the sof and the sopcinfo file generation to build the custom hardware on altera monitor program. In the project you need to develop an nios program using bios assembly language where it displays hello on the display of fpga de2115 board cyclo...
it uses a FPGA board to program the cpu on it and you should make an audiometer for it using Quartus and NIOS II also you need DE2-115 board the info is in the attachment
...Project, we need Data Acquisition from Sensors to DE2-115 Developmental board by FPGA implement EtherCAT slave and via an ADC.rnrnDescription:rnrnWe need to implement an over sampling ADC for an interface between Sensor and the developmental board ( DE2-115). mostly 16 bit. SPI interface is already used, so look for another one.rn There is an CODEC ( WM 8731 ) but audio already available on DE2-115, in case it useful.rnrnThen for Data acquisition, DE 2-115 board need to be implemented as EtherCAT slave, and data to be store in Dual - Port RAM, with bit rate of 40 GBPS, if possible more.rnrnIts a data acquisition project, the data from Sensors are fed to TI controller via FPGA board.rnrnlet me knw, in case of additional details...
Write code for FPGA (Lattice) in Verilog (required this specific language) for 8-bit parallel input data acquisition from ADC (8-bit ADC MAX1192), data processing (8-bit ADC data from baseband), and data sending (SPI, RS-232, etc). The 8-bit parallel data will be coming from RF base band to FPGA. It is required to sample ADC (MAX1192) at specific CLK frequency, receive data from it. During data receive specific preamble needs to be found. Data following the preamble has to be received, processed and output to SPI or serial (USB). Upon completion first part of the project (above) additional project input and support may be required (separate contract and compensation). MAX1192 datasheet:
Embedded software development, bringing up Cyclone 5 FPGA with dual ARM Cortex processessors
i have to create digital signal generator using fpga with different voltages and different frequecies. i have the digital to analog converter pheripheral board compatible with my basys 3 development board. the dilient da2 board already give the verilog code for the module i want ur help to generate different waves forms with different voltages and frequecie
Create digital signal generator using fpga with different voltages and different frequecies with digital to analog converter pheripheral board compatible with my basys 3 development board. Have Digilent da2 board verilog code for the module.
need some expert to configure GTP transceiver in Sparten6 Sp605 FPGA board to and GTX transceiver in Kintex7 KC705 FPGA board to communicate with each other. It is just a matter of configuration. contact any one who have alredy have experience in GTP/ GTX transceiver configuration. Other do no bother plz. no time for experimentation.........
Digital signal generator verilog code need to create using fpga basys 3 development board and digilent pmon DA2 board.
Necesito para nuestro equipo de 15 ingenieros incorporar dos nuevos ingenieros con ilusión, cierta experiencia y conocimientos en VHDL/Verilog y microprocesadores. Es trabajo a tiempo completo y con estabilidad (2 años). Ubicación: Sevilla y Albacete. Uno en cada sitio.
fpga/ultra and xilinx wiznet vhdl/verilog
Hello, I need a VHDL design which converts the complete DDR3 SDRAM Memory to a 5-Bit FIFO. The target Memory is Micron MT47H32M16HR -25 or -3 speed grade. Target FPGA is Xilinx Spartan 6 XC6SLX9-2CSG324C. Design should work in Xilinx ISE 14.7 Simulator. Attached is the TOP VHDL file to give an idea how it looks like.
I am looking for a freelancer to help me with my project. The skills required are Algorithm, FPGA, Matlab and Mathematica and Verilog / VHDL. I am happy to pay a fixed priced and my budget is £250 - £750 GBP. I have not provided a detailed description and have not uploaded any files.
I need to read data from Excel and run it on FPGA (Compact RIO). Then out the result as anologue output then view it from Scope
I need you to develop some software for me. I would like this software to be developed for Windows . Detailed Description: i want to make a Labview program to retrieve data from National Instrument (FPGA) RIO at time interval of 0.1 second The software should have basic functionalities of monitoring/displaying basic parameters of instruments and recording data into hard disk. We could discuss at length if you are interested in this project.
Face Recognition using Eigenfaces in FPGA HDL : Verilog Softwares: Modelsim, ALTERA Quartus II FPGA: ALTERA Cyclone II Need to simulate and synthesize eigenfaces for face-recognition in a FPGA. Eigenfaces for recognition by Matthew Turk and Alex Pentland ( IEEE paper) is the core of this project. Eigenfaces method is the core of this project, which is explained in detail in Eigenfaces for recognition by Matthew Turk and Alex Pentland. This method has been implemented successfully in MATLAB and the code is also freely available, but it has not been implemented in FPGA's extensively due to the memory and processing speed constrains. The Pixel information from greyscale face images (up to 5 images can be used & face images should be from appr...
frame synchronization code in vhdl or vlsi
We own a few GSM Gateways and we would like to be able to send AT commands directly to the GSM module. The only way to do that is using UART from the ARM11 Chip to GSM module. The embedded busybox includes microcom to which we have access. For this project, it req...embedded busybox includes microcom to which we have access. For this project, it requires some reverse engineering skills in Linux embedded system. It's a little more complicate because the embedded ARM communicates to GSM modules trough FGPA chip. So what we probably need first is to find and read the UART connection between FPGA and ARM chip. We already have some decompiled code in which there is communication between the main ARM chip and GSM Module trough FPGA. We can give you remote access d...
Design using Verilog, implement on Artix-7 XC7A100T-CSG324 chip, and tested within Xilinx development environment a Fast Fourier transform (FFT) algorithm. Code must be clear, well commented, and delivered with testing results. I will testing the function of the project FFT against Xilinx Vivado's build in FFT function prior to declaring project complete.
I am looking for a freelancer to help me with my project. The skills required are Arduino, Bluetooth Low Energy (BLE), FPGA and Microcontroller. I am happy to pay a fixed priced and my budget is $250 - $750 USD. I have not provided a detailed description and have not uploaded any files.
Need a simple pong game based around a certain FPGA board and Quartus II software. Will provide more information upon request.
